The present invention relates to a semiconductor integrated circuit device and a fabrication technique of a semiconductor integrated circuit device, particularly to a technique effective when adapted to the connection between metallizations of a semiconductor integrated circuit device or connection between a semiconductor substrate and a metallization.
With a recent tendency to high integration of LSI, a multilayer metallization structure having metallizations and insulating films formed alternately in repetition has been adopted. Such plural metallizations or a semiconductor substrate and a metallization are connected through an electroconductive portion (plug or the like) formed in the contact hole in an interlayer insulating film.
In Japanese Patent Application Laid-Open No. Hei 11(1999)-87353, disclosed is a technique for forming an electroconductive plug by forming, in a connecting hole CH and over a copper metallization 11, a TiN film 12 serving effectively as a barrier layer by long throw sputtering, depositing thereover a W layer, and polishing a tungsten layer 13 and the TiN layer by CMP.
In Japanese Patent Application Laid-Open No. Hei 8(1996)-181212, disclosed is a technique for forming a second metallization film in order to prevent peeling of a TiN film and improve barrier properties, which is attained by annealing a Ti film, which has been formed in a contact hole, by collimation sputtering, forming a TiN film 23, forming thereover a reactive sputter TiN film 24 and then depositing a W film 12 by CVD.
In Japanese Patent Application Laid-Open No. Hei 10(1998)-242271, disclosed is a technique (FIG. 4) for securing the contact between a connecting plug and groove metallization by forming a connecting plug 45, making a metallization groove 46 in such a way that the connecting plug 45 invades the metallization groove 46, forming a TiN/Ti film as an underlying film 47 by LD sputtering, and forming a Cu layer 48a, thereby forming a groove metallization 48.
In Japanese Patent Application Laid-Open No. Hei 6(1994)-140359, disclosed is a technique for forming, in a contact hole 50 and over a BPSG film 30, a layer 40 from a sputter target 70 through a collimator 60 by chemical reactive sputtering.
In Japanese Patent Application Laid-Open No. Hei 4(1992)-207033, disclosed is a technique for attaining good filling of a via hole and planarization of a metallization layer, which comprises depositing a first electroconductive film on the bottom of the via hole by high-temperature/high-bias or high-temperature sputtering, or selective metal CVD and then depositing thereover a second electroconductive film by traditional sputtering and vapor deposition.
In Japanese Patent Application Laid-Open No. Hei 4(1992)-207033, disclosed is a technique for constituting a plug 5 from a barrier film 5a obtained by depositing titanium or titanium nitride by sputtering, an underlying film 5b obtained by depositing tungsten over the barrier film 5a by sputtering and a filling film 5c obtained by depositing a tungsten film by CVD for filling therewith an opening.